Persistent Link:
http://hdl.handle.net/10150/184687
Title:
Synchronous fault simulation by surrogate with exceptions.
Author:
Wang, Xiaolin.
Issue Date:
1989
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
The contribution of this dissertation is the development of a completely new and accurate algorithm SFSSE for synchronous fault simulation of sequential circuits. The distinctive difference between SFSSE (Synchronous Fault Simulation by Surrogate with Exceptions) and similar approaches for fault simulation in combinational logic circuits is that SFSSE is capable of handling faults stored in more than one memory elements and the reconvergence over time of the stored fault effect with the original fault. The experimental result shows a significant improvement for SFSSE by comparing its execution time to that of parallel fault simulation. After a stored fault list is established during one clock period, all paths from the output of that memory element to the primary outputs might be blocked in subsequent clock periods. A fault is usually propagated through many paths in various subnetworks over several clock periods, and it is detected when only one of these paths reaches a primary output. A new idea for efficiency is suggested in the last chapter to avoid the unproductive simulation activity. In that approach the waste of simulation time is avoided by overlapping the simulation of multiple clock periods.
Type:
text; Dissertation-Reproduction (electronic)
Keywords:
Electric fault location.; Integrated circuits.; Computer simulation.
Degree Name:
Ph.D.
Degree Level:
doctoral
Degree Program:
Electrical and Computer Engineering; Graduate College
Degree Grantor:
University of Arizona
Advisor:
Hill, Frederick J.

Full metadata record

DC FieldValue Language
dc.language.isoenen_US
dc.titleSynchronous fault simulation by surrogate with exceptions.en_US
dc.creatorWang, Xiaolin.en_US
dc.contributor.authorWang, Xiaolin.en_US
dc.date.issued1989en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractThe contribution of this dissertation is the development of a completely new and accurate algorithm SFSSE for synchronous fault simulation of sequential circuits. The distinctive difference between SFSSE (Synchronous Fault Simulation by Surrogate with Exceptions) and similar approaches for fault simulation in combinational logic circuits is that SFSSE is capable of handling faults stored in more than one memory elements and the reconvergence over time of the stored fault effect with the original fault. The experimental result shows a significant improvement for SFSSE by comparing its execution time to that of parallel fault simulation. After a stored fault list is established during one clock period, all paths from the output of that memory element to the primary outputs might be blocked in subsequent clock periods. A fault is usually propagated through many paths in various subnetworks over several clock periods, and it is detected when only one of these paths reaches a primary output. A new idea for efficiency is suggested in the last chapter to avoid the unproductive simulation activity. In that approach the waste of simulation time is avoided by overlapping the simulation of multiple clock periods.en_US
dc.typetexten_US
dc.typeDissertation-Reproduction (electronic)en_US
dc.subjectElectric fault location.en_US
dc.subjectIntegrated circuits.en_US
dc.subjectComputer simulation.en_US
thesis.degree.namePh.D.en_US
thesis.degree.leveldoctoralen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.contributor.advisorHill, Frederick J.en_US
dc.identifier.proquest8915993en_US
dc.identifier.oclc702371855en_US
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