Persistent Link:
http://hdl.handle.net/10150/184085
Title:
PUNCH-THROUGH SPACE-CHARGE LIMITED LOADS (RESISTORS).
Author:
MUSALLAM, ALI ABDULKAREEM.
Issue Date:
1987
Publisher:
The University of Arizona.
Rights:
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
Abstract:
There are several important semiconductor devices in which the transport of carriers is controlled by punch-through space-charge effects. Examples include the Bipolar Mode Static Induction Transistor (BSIT), ultrasmall Punch-through MOSFETs, and BARITT diodes for microwave applications. The development of punch-through space-charge type of devices is a technology motivated by the demanding high density among the IC chips. This dissertation discusses a device which operates in a punch-through condition with space-charge control of currents. It is a two terminal device, which could be fabricated with no deviation from today's technology. The device structure is simple, with two n⁺ or p⁺ regions formed in p⁻ or n⁻ substrate, respectively. Punch-through space-charge limited structures both n⁺p⁻n⁺ and p⁺n⁻p⁺, were simulated using a general one-dimensional semiconductor device performance simulation program GESIM1 for dynamic and static analysis. The results of simulation show that the potential barrier height decreases with increasing applied potential and with a reduction of the spacing L between the n⁺ diffusion in an n⁺p⁻n⁺ structure. The resistance increases as the spacing L is increased. A two-dimensional analytical model of carrier transport in the device was developed. This model accounts for surface effects as well as the space-charge limited flow. Also, a one-dimensional model that includes mobile carriers effects on the device operation. Structures of various configurations were fabricated and tested. Electrical evaluations of these structures provided large value resistors in a remarkably small area compare to traditional integrated resistors. The resistance was observed to increase with the spacing L and with the resistivity of the starting substrate. These punch-through space-charge limited loads should have applications as an alternative approach for integrated resistors in high-speed VLSI applications. They can provide very small area, large value resistors based on the space-charge limiting action of the device. The range of resistance value is large, and small dimensions lead to small capacitance and fast switching times.
Type:
text; Dissertation-Reproduction (electronic)
Keywords:
Semiconductors.; Integrated circuits.
Degree Name:
Ph.D.
Degree Level:
doctoral
Degree Program:
Electrical and Computer Engineering; Graduate College
Degree Grantor:
University of Arizona
Advisor:
Mattson, Roy H.

Full metadata record

DC FieldValue Language
dc.language.isoenen_US
dc.titlePUNCH-THROUGH SPACE-CHARGE LIMITED LOADS (RESISTORS).en_US
dc.creatorMUSALLAM, ALI ABDULKAREEM.en_US
dc.contributor.authorMUSALLAM, ALI ABDULKAREEM.en_US
dc.date.issued1987en_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.description.abstractThere are several important semiconductor devices in which the transport of carriers is controlled by punch-through space-charge effects. Examples include the Bipolar Mode Static Induction Transistor (BSIT), ultrasmall Punch-through MOSFETs, and BARITT diodes for microwave applications. The development of punch-through space-charge type of devices is a technology motivated by the demanding high density among the IC chips. This dissertation discusses a device which operates in a punch-through condition with space-charge control of currents. It is a two terminal device, which could be fabricated with no deviation from today's technology. The device structure is simple, with two n⁺ or p⁺ regions formed in p⁻ or n⁻ substrate, respectively. Punch-through space-charge limited structures both n⁺p⁻n⁺ and p⁺n⁻p⁺, were simulated using a general one-dimensional semiconductor device performance simulation program GESIM1 for dynamic and static analysis. The results of simulation show that the potential barrier height decreases with increasing applied potential and with a reduction of the spacing L between the n⁺ diffusion in an n⁺p⁻n⁺ structure. The resistance increases as the spacing L is increased. A two-dimensional analytical model of carrier transport in the device was developed. This model accounts for surface effects as well as the space-charge limited flow. Also, a one-dimensional model that includes mobile carriers effects on the device operation. Structures of various configurations were fabricated and tested. Electrical evaluations of these structures provided large value resistors in a remarkably small area compare to traditional integrated resistors. The resistance was observed to increase with the spacing L and with the resistivity of the starting substrate. These punch-through space-charge limited loads should have applications as an alternative approach for integrated resistors in high-speed VLSI applications. They can provide very small area, large value resistors based on the space-charge limiting action of the device. The range of resistance value is large, and small dimensions lead to small capacitance and fast switching times.en_US
dc.typetexten_US
dc.typeDissertation-Reproduction (electronic)en_US
dc.subjectSemiconductors.en_US
dc.subjectIntegrated circuits.en_US
thesis.degree.namePh.D.en_US
thesis.degree.leveldoctoralen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.grantorUniversity of Arizonaen_US
dc.contributor.advisorMattson, Roy H.en_US
dc.contributor.committeememberWilamowski, B. M.en_US
dc.contributor.committeememberStaszak, Z. J.en_US
dc.contributor.committeememberJain, S. C.en_US
dc.identifier.proquest8712899en_US
dc.identifier.oclc698475182en_US
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